The receiver interested in the transmitted bit stream must
perform two tasks when received waveform
rt
r
t
begins.
-
It must determine when bit boundaries occur: The receiver
needs to synchronize with the transmitted
signal. Because transmitter and receiver are designed in
concert, both use the same value for the bit interval
TT. Synchronization can occur
because the transmitter begins sending with a reference bit
sequence, known as the preamble. This
reference bit sequence is usually the alternating sequence
as shown in the square wave example and in the FSK
example. The receiver knows what the preamble bit
sequence is and uses it to determine when bit boundaries
occur. This procedure amounts to what in digital hardware
as self-clocking signaling: The receiver of a
bit stream must derive the clock — when bit boundaries
occur — from its input signal. Because the receiver
usually does not determine which bit was sent until
synchronization occurs, it does not know when during the
preamble it obtained synchronization. The transmitter
signals the end of the preamble by switching to a second bit
sequence. The second preamble phase informs the receiver
that data bits are about to come and that the preamble is
almost over.
-
Once synchronized and data bits are transmitted, the
receiver must then determine every T
T seconds what bit was transmitted during the
previous bit interval. We focus on this aspect of the
digital receiver because this strategy is also used in
synchronization.
The receiver for digital communication is known as a
matched filter.
This receiver, shown in
Figure 1,
multiplies the received signal by each of the possible members
of the transmitter signal set, integrates the product over the
bit interval, and compares the results. Whichever path through
the receiver yields the largest value corresponds to the
receiver's decision as to what bit was sent during the previous
bit interval. For the next bit interval, the multiplication and
integration begins again, with the next bit decision made at the
end of the bit interval. Mathematically, the received value of
bn
b
n
, which we label
b
^
n
b
^
n
, is given by
b
^
n=argmaxi∫nT(n+1)Trt s i
tdt
b
^
n
i
t
n
1
T
n T
r t
s i
t
(1)
You may not have seen the
argmaxi
i
notation before.
maxii·
i
·
yields the maximum value of its argument with respect to the index
i
i.
argmaxi
i
equals the value of the index that yields the maximum.
Note that the precise numerical value of the integrator's output
does not matter; what does matter is its value relative to the
other integrator's output.
Let's assume a perfect channel for the moment: The received
signal equals the transmitted one. If bit 0 were sent using the
baseband BPSK signal set, the integrator outputs would be
∫nT(n+1)Trt
s
0
tdt=A2T
t
n
1
T
n
T
r
t
s
0
t
A
2
T
(2)
If bit 1 were sent,
∫nT(n+1)Trt
s
0
tdt=−(A2T)
t
n
1
T
n
T
r
t
s
0
t
A
2
T
(3)
Can you develop a receiver for BPSK signal sets that
requires only one multiplier-integrator combination?
In BPSK, the signals are negatives of each other:
s
1
t=−
s
0
t
s
1
t
s
0
t
. Consequently, the output of each
multiplier-integrator combination is the negative of the
other. Choosing the largest therefore amounts to choosing
which one is positive. We only need to calculate one of
these. If it is positive, we are done. If it is negative,
we choose the other signal.
What is the corresponding result when the
amplitude-modulated BPSK signal set is used?
The matched filter outputs are
±A2T2
±
A
2
T
2
because the sinusoid has less power than a pulse having the
same amplitude.
Clearly, this receiver would always choose the bit correctly.
Channel attenuation would not affect this correctness; it would
only make the values smaller, but all that matters is which is
largest.
"Electrical Engineering Digital Processing Systems in Braille."